US Patent No: 7,274,214

Number of patents in Portfolio can not be more than 2000

Efficient tile layout for a programmable logic device

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Abstract

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In an integrated circuit including an array of substantially similar tiles, a tile includes a logic block and at least one column of routing multiplexers driving interconnect lines that can be used to programmably interconnect the logic blocks. An output terminal of the logic block drives a vertically adjacent subset of the routing multiplexers in the column. Optionally, the tile also includes a second column of routing multiplexers. The logic block output terminal also drives a vertically adjacent subset of the routing multiplexers in the second column, and in some embodiments the two subsets are physically located in horizontal alignment with one another within the tile. The tile can also include a column of input multiplexers for the logic block. The logic block output terminal also drives a vertically adjacent subset of the input multiplexers, and the subsets of routing multiplexers and input multiplexers can be horizontally aligned within the tile.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
XILINX, INC.SAN JOSE, CA3307

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Young, Steven P Boulder, CO 240 5009

Cited Art Landscape

Patent Info (Count) # Cites Year
 
XILINX, INC. (39)
5,629,886 Method and structure for providing fast propagation of a carry signal in a field programmable gate array 58 1995
5,546,018 Fast carry structure with synchronous input 137 1995
5,801,546 Interconnect architecture for field programmable gate array using variable length conductors 83 1996
5,889,413 Lookup tables which double as shift registers 70 1996
5,818,730 FPGA one turn routing structure and method using minimum diffusion area 6 1996
5,828,230 FPGA two turn routing structure with lane changing and minimum diffusion area 45 1997
6,427,156 Configurable logic block with AND gate for efficient multiplication in FPGAS 76 1997
5,914,616 FPGA repeatable interconnect structure with hierarchical interconnect lines 357 1997
5,889,411 FPGA having logic element carry chains capable of generating wide XOR functions 188 1997
5,942,913 FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines 64 1997
5,963,050 Configurable logic element with fast feedback paths 101 1997
5,920,202 Configurable logic element with ability to evaluate five and six input functions 82 1997
6,069,490 Routing architecture using a direct connect routing mesh 175 1997
6,086,629 Method for design implementation of routing in an FPGA using placement directives such as local outputs and virtual buffers 38 1997
5,907,248 FPGA interconnect structure with high-speed high fanout capability 43 1998
6,081,914 Method for implementing priority encoders using FPGA carry logic 27 1998
6,184,709 Programmable logic device having a composable memory array overlaying a CLB array 106 1998
6,188,091 FPGA one turn routing structure using minimum diffusion area 4 1998
6,163,167 Method for generating an FPGA two turn routing structure with lane changing and minimum diffusion area 3 1998
6,157,209 Loadable up-down counter with asynchronous reset 37 1998
6,184,712 FPGA configurable logic block with multi-purpose logic/memory circuit 45 1999
6,154,053 Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch 48 1999
6,107,827 FPGA CLE with two independent carry chains 44 1999
6,204,689 Input/output interconnect circuit for FPGAs 68 1999
6,396,303 Expandable interconnect structure for FPGAS 66 1999
6,124,731 Configurable logic element with ability to evaluate wide logic functions 28 2000
6,204,690 FPGA architecture with offset interconnect lines 32 2000
6,288,570 Logic structure and circuit for fast carry 46 2000
6,466,052 Implementing wide multiplexers in an FPGA using a horizontal chain structure 21 2001
6,396,302 Configurable logic element with expander structures 73 2001
6,448,808 Interconnect structure for a programmable logic device 119 2001
6,630,841 Configurable logic element with expander structures 13 2002
6,708,191 Configurable logic block with and gate for efficient multiplication in FPGAS 22 2002
6,829,756 Programmable logic device with time-multiplexed interconnect 152 2002
7,111,214 Circuits and methods for testing programmable logic devices using lookup tables and carry chains 13 2002
6,621,296 FPGA lookup table with high speed read decorder 18 2002
6,847,228 Carry logic design having simplified timing modeling for a field programmable gate array 10 2002
6,943,581 Test methodology for direct interconnect with multiple fan-outs 8 2003
7,138,820 System monitor in a programmable logic device 35 2004
 
ALTERA CORPORATION (18)
5,761,099 Programmable logic array integrated circuits with enhanced carry routing 56 1995
5,850,152 Programmable logic array integrated circuit devices 59 1997
6,107,822 Logic element for a programmable logic integrated circuit 36 1998
6,122,720 Coarse-grained look-up table architecture 33 1998
2001/0048,320 Programmable logic device logic modules with shift register capabilities 17 2001
6,452,834 2T dual-port DRAM in a pure logic process with non-destructive read capability 16 2001
2001/0006,347 Redundancy circuitry for programmable logic devices with interleaved input circuits 20 2001
2002/0057,103 Interconnection and input/output resources for programable logic integrated circuit devices 13 2002
6,646,467 PCI-compatible programmable logic devices 9 2002
6,747,480 Programmable logic devices with bidirect ional cascades 26 2002
6,987,401 Compare, select, sort, and median-filter apparatus in programmable logic devices and associated methods 6 2002
6,937,064 Versatile logic element and logic array block 19 2002
6,943,580 Fracturable lookup table and logic element 32 2003
6,873,181 Automated implementation of non-arithmetic operators in an arithmetic logic cell 16 2003
2005/0038,844 Programmable logic device including multipliers and configurations thereof to reduce resource utilization 10 2003
7,061,268 Initializing a carry chain in a programmable logic device 19 2004
7,030,652 LUT-based logic element with support for Shannon decomposition and associated method 12 2004
2005/0127,944 Versatile logic element and logic array block 22 2005
 
LATTICE SEMICONDUCTOR CORPORATION (4)
5,381,058 FPGA having PFU with programmable output driver inputs 47 1993
6,380,759 Variable grain architecture for FPGA integrated circuits 40 2000
6,605,959 Structure and method for implementing wide multiplexers 10 2001
2005/0093,577 Multiplexer circuits 11 2003
 
CYPRESS SEMICONDUCTOR CORPORATION (2)
6,201,408 Hybrid product term and look-up table-based programmable logic device with improved speed and area efficiency 12 1998
6,201,409 High performance product term based carry chain scheme 16 2000
 
ACTEL CORPORATION (1)
5,698,992 Programmable logic module and architecture for field programmable gate array device 26 1996
 
ALTERA CANADA CO. (1)
6,828,824 Heterogeneous interconnection architecture for programmable logic devices 50 2003
 
KILOPASS TECHNOLOGY, INC. (1)
2005/0218,929 Field programmable gate array logic cell and its derivatives 11 2004
 
MARVELL SEMICONDUCTOR, INC. (1)
6,515,506 Circuit for reducing pin count of a semiconductor chip and method for configuring the chip 13 2000
 
NEC CORPORATION (1)
6,836,147 Function block 16 2002
 
QUICKLOGIC CORPORATION (1)
5,986,468 Programmable application specific integrated circuit and logic cell therefor 11 1997
 
VENTURE LENDING & LEASING IV, V (1)
2006/0164,120 Programmable logic cells with Local Connections 11 2005

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
XILINX, INC. (5)
7,498,192 Methods of providing a family of related integrated circuits of different sizes 3 2006
7,491,576 Yield-enhancing methods of providing a family of scaled integrated circuits 2 2006
7,451,421 Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies 5 2006
7,402,443 Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes 4 2006
8,001,511 Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies 8 2008
 
ALTERA CORPORATION (3)
7,394,287 Programmable logic device having complex logic blocks with improved logic cell functionality 3 2007
7,459,932 Programmable logic device having logic modules with improved register capabilities 1 2007
7,675,319 Programmable logic device having complex logic blocks with improved logic cell functionality 1 2008
 
Other [Check patent profile for assignment information] (1)
8,869,088 Oversized interposer formed from a multi-pattern region mask 0 2012

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