Method and apparatus to counter mismatched burst lengths
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United States of America Patent
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Oct 9, 2007
Grant Date -
Jun 30, 2005
app pub date -
Dec 31, 2003
filing date -
Dec 31, 2003
priority date (Note) -
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Abstract
Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently operable enough to support unrelated transactions with each group, and can be used to stagger read operations with shortened burst transfers so as to minimize dead time on a memory bus.
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