Integrated circuit structure and a design method thereof
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United States of America Patent
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Oct 9, 2007
Grant Date -
Feb 3, 2005
app pub date -
Jan 21, 2004
filing date -
Jul 22, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention discloses an integrated circuit structure and a design method thereof, in which a circuit passageway is arranged at each circuit element terminal in circuit design stage. The arranged circuit passageway does not only increase layout flexibility in circuit simulation stage but also simplify layout difficulty when the circuit layout needs to be modified after taping out stage. Also, the circuit passageway can minimize modified metal layers, i.e. the number of modified masks is minimized. Because the expense of fab is based on the utilized layers and number of masks instead of designs of masks, the present invention will not increase the expense in taping out stage and can save the cost of research and development when modifications are required.
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