Importance

Loading Importance Indicators...

Abstract

A memory device comprises a memory cell array (1) with a multitude of memory cells (111). Each of the memory cells (111) is assigned to one of a multitude of blocks (15). Each memory cell (111) is accessible by an access signal in order to alter stored information. Each of the memory cells (111) is assigned to one of a multitude of blocks (15). The memory device further comprises a measuring unit (100) coupled to the memory cell array (1) and being operable to identify a selected access characteristic of each of the memory cells (11) and an assignment unit (150) which is coupled to the measuring unit (100) and is operable to assign a performance parameter (215) to each block (15). A performance memory unit (2) is adapted to contain the performance parameters (215) assigned to the blocks (15).

Loading the Abstract Image...

First Claim