US Patent No: 7,283,410

Number of patents in Portfolio can not be more than 2000

Real-time adaptive SRAM array for high SEU immunity

ALSO PUBLISHED AS: 20070211527

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Abstract

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A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
GOOGLE INC.MOUNTAIN VIEW, CA13016

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hsu, Louis L Fishkill, NY 296 5347
Mandelman, Jack A Flat Rock, NC 370 7629
Wong, Robert C Poughkeepsie, NY 58 498
Yang, Chih-Chao Poughkeepsie, NY 402 1025

Cited Art Landscape

Patent Info (Count) # Cites Year
 
THOMSON & NIELSEN ELECTRONICS LTD. (1)
4,983,843 Radon detector 11 1989
 
T-RAM (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC (1)
6,785,169 Memory cell error recovery 46 2002
 
SCIENCE AND TECHNOLOGY CORPORATION (1)
6,583,470 Radiation tolerant back biased CMOS VLSI 17 2000
 
UNITED STATES AIR FORCE (1)
* 5,657,267 Dynamic RAM (random access memory) with SEU (single event upset) detection 7 1995
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
ARM LIMITED (2)
* 8,732,523 Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus 0 2011
* 2013/0103,972 Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus 0 2011
 
CYPRESS SEMICONDUCTOR CORPORATION (30)
8,149,048 Apparatus and method for programmable power management in a programmable analog circuit block 4 2001
8,176,296 Programmable microcontroller architecture 4 2001
8,160,864 In-circuit emulator and pod synchronized boot 0 2001
8,103,496 Breakpoint control in an in-circuit emulation system 6 2001
8,078,970 Graphical user interface with user-selectable list-box 3 2001
8,069,405 User interface for efficiently browsing an electronic document using data-driven tabs 4 2001
8,103,497 External interface for event architecture 5 2002
8,085,067 Differential-to-single ended signal converter circuit and method 5 2006
8,067,948 Input/output multiplexer bus 8 2007
8,049,569 Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes 4 2007
* 8,111,577 System comprising a state-monitoring memory element 4 2007
8,064,281 System comprising a state-monitoring memory element 0 2007
8,092,083 Temperature sensor with digital bandgap 1 2007
8,402,313 Reconfigurable testing system and method 1 2007
8,026,739 System level interconnect with programmable switching 22 2007
8,085,100 Poly-phase frequency synthesis oscillator 1 2008
8,078,894 Power management architecture, method and configuration system 10 2008
8,040,266 Programmable sigma-delta analog-to-digital converter 3 2008
8,130,025 Numerical band gap 2 2008
8,120,408 Voltage controlled oscillator delay cell and method 1 2008
8,358,150 Programmable microcontroller architecture(mixed analog/digital) 4 2010
8,555,032 Microcontroller programmable system on a chip with programmable interconnect 2 2011
8,499,270 Configuration of programmable IC design elements 1 2011
8,909,960 Power management architecture, method and configuration system 0 2011
8,476,928 System level interconnect with programmable switching 1 2011
* 8,462,576 State-monitoring memory element 0 2011
8,717,042 Input/output multiplexer bus 0 2011
8,736,303 PSOC architecture 0 2011
* 8,705,309 State-monitoring memory element 0 2013
* 2013/0336,081 STATE-MONITORING MEMORY ELEMENT 0 2013
 
ALTERA CORPORATION (1)
* 8,705,300 Memory array circuitry with stability enhancement features 4 2010
 
NATIONAL CHUNG CHENG UNIVERSITY (2)
* 8,743,592 Memory circuit properly workable under low working voltage 0 2012
* 2013/0314,977 MEMORY CIRCUIT PROPERLY WORKABLE UNDER LOW WORKING VOLTAGE 0 2012
 
SANDISK TECHNOLOGIES INC. (3)
8,897,085 Immunity against temporary and short power drops in non-volatile memory: pausing techniques 0 2013
* 8,817,569 Immunity against temporary and short power drops in non-volatile memory 0 2013
* 2013/0265,841 Immunity Against Temporary and Short Power Drops in Non-Volatile Memory 1 2013
 
Ryan Technologies, LLC (1)
7,961,501 Radiation sensors and single-event-effects suppression devices 5 2009
* Cited By Examiner

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