Real-time adaptive SRAM array for high SEU immunity

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7283410
APP PUB NO 20070211527A1
SERIAL NO

11308215

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
GOOGLE LLCMOUNTAIN VIEW, CA13738

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hsu, Louis L Fishkill, NY 299 6814
Mandelman, Jack A Flat Rock, NC 372 9445
Wong, Robert C Poughkeepsie, NY 65 845
Yang, Chih-Chao Poughkeepsie, NY 449 2844

Cited Art Landscape

Patent Info (Count) # Cites Year
 
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T-RAM (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC (1)
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SCIENCE & TECHNOLOGY CORPORATION @ UNM (1)
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The United States of America as represented by the Secretary of the Air Force (1)
* 5657267 Dynamic RAM (random access memory) with SEU (single event upset) detection 8 1995
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
9767917 Mitigation scheme for SRAM functionality 0 2015
 
ARM LIMITED (3)
* 8732523 Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus 1 2011
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9116844 Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus 0 2014
 
CYPRESS SEMICONDUCTOR CORPORATION (18)
8149048 Apparatus and method for programmable power management in a programmable analog circuit block 4 2001
8176296 Programmable microcontroller architecture 12 2001
8067948 Input/output multiplexer bus 21 2007
8064281 System comprising a state-monitoring memory element 0 2007
8092083 Temperature sensor with digital bandgap 5 2007
8026739 System level interconnect with programmable switching 34 2007
8078894 Power management architecture, method and configuration system 15 2008
9720805 System and method for controlling a target device 0 2008
8040266 Programmable sigma-delta analog-to-digital converter 4 2008
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8358150 Programmable microcontroller architecture(mixed analog/digital) 8 2010
8555032 Microcontroller programmable system on a chip with programmable interconnect 6 2011
8499270 Configuration of programmable IC design elements 4 2011
8909960 Power management architecture, method and configuration system 2 2011
8476928 System level interconnect with programmable switching 4 2011
8717042 Input/output multiplexer bus 1 2011
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SANDISK TECHNOLOGIES LLC (4)
9329986 Peak current management in multi-die non-volatile memory devices 0 2013
8897085 Immunity against temporary and short power drops in non-volatile memory: pausing techniques 1 2013
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MONTEREY RESEARCH, LLC (14)
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ALTERA CORPORATION (1)
* 8705300 Memory array circuitry with stability enhancement features 4 2010
 
NATIONAL CHUNG CHENG UNIVERSITY (2)
* 8743592 Memory circuit properly workable under low working voltage 0 2012
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Ryan Technologies, LLC (1)
7961501 Radiation sensors and single-event-effects suppression devices 5 2009
* Cited By Examiner

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