Digital data processing apparatus having multi-level register file
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United States of America Patent
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Oct 16, 2007
Grant Date -
Dec 29, 2005
app pub date -
Jun 24, 2004
filing date -
Jun 24, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.
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