System and method for testing write strobe timing margins in memory devices
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United States of America Patent
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Oct 16, 2007
Grant Date -
Jun 14, 2007
app pub date -
Dec 8, 2005
filing date -
Dec 8, 2005
priority date (Note) -
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Abstract
Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the transition times of respective transmitter clock signals. When enabled, a transmitter uses the transmitter clock signals to transmit a write data strobe signal corresponding to the first and second digital signals to memory devices being tested. The transmitter is enabled by an enable signal generated by a third phase interpolator. By varying the timing of the enable signal, the third phase interpolator can vary the duration of preambles and postambles of respective write data strobe signals.
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