Configuration circuits for programmable logic devices
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United States of America Patent
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Oct 23, 2007
Issued Date -
N/A
app pub date -
Mar 2, 2006
filing date -
Jul 8, 2002
priority date (Note) -
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Abstract
Configuration circuits wherein configurable elements comprise low conducting on currents and/or low on to off current ratios for programmable logic devices are disclosed. A semiconductor device, wherein: a programmable logic circuit is configured by a control signal received at a capacitive node in the circuit, wherein the control signal is further generated by one of: a low conducting current pull-up configurable element configured to couple the control signal to a power supply voltage; and a low conducting current pull-down configurable element configured to couple the control signal to a ground supply voltage; wherein, the low conducting current charge the capacitive node to either the power or ground voltage levels.
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