Method for controlled programming of non-volatile memory exhibiting bit line coupling
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United States of America Patent
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Oct 23, 2007
Grant Date -
Apr 19, 2007
app pub date -
Oct 14, 2005
filing date -
Oct 14, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.
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