US Patent No: 7,286,441

Number of patents in Portfolio can not be more than 2000

Integrated memory controller

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Abstract

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A memory system comprises a memory that includes at least one of Synchronous Dynamic Random Access Memory (SDRAM) and Double Data Rate SDRAM (DDR). A memory controller communicates with the memory, generates an SDRAM clock signal, and receives a bi-directional sampling clock signal (DQS). When the memory includes the DDR, the memory generates the DQS. When the memory includes the SDRAM, the DQS is based on the SDRAM clock signal.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
MARVELL INTERNATIONAL LTD.HAMILTON4662

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jayabharathi, Dinesh Orange, CA 7 17
White, Theodore C Rancho Santa Margarita, CA 24 445

Cited Art Landscape

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* Cited By Examiner

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (1)
9,171,846 Leakage and performance graded memory 0 2012
 
REALTEK SEMICONDUCTOR CORP. (2)
* 7,652,936 Signal sampling apparatus and method for DRAM memory 0 2007
* 2007/0201,300 SIGNAL SAMPLING APPARATUS AND METHOD FOR DRAM MEMORY 2 2007
 
HULU, LLC (1)
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* Cited By Examiner

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