
US Patent No: 7,286,441
Number of patents in Portfolio can not be more than 2000
Integrated memory controller
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Oct 23, 2007
Issued date -
Oct 4, 2006
filing date -
11/542,862
serial no -
In Force
status
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Abstract
A memory system comprises a memory that includes at least one of Synchronous Dynamic Random Access Memory (SDRAM) and Double Data Rate SDRAM (DDR). A memory controller communicates with the memory, generates an SDRAM clock signal, and receives a bi-directional sampling clock signal (DQS). When the memory includes the DDR, the memory generates the DQS. When the memory includes the SDRAM, the DQS is based on the SDRAM clock signal.
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First Claim
Related Publications
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Apr 23, 2015 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Apr 23, 2019 |
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge - 7.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |