Integrated memory controller
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United States of America Patent
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Oct 23, 2007
Grant Date -
N/A
app pub date -
Oct 4, 2006
filing date -
Jun 14, 2004
priority date (Note) -
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Abstract
A memory system comprises a memory that includes at least one of Synchronous Dynamic Random Access Memory (SDRAM) and Double Data Rate SDRAM (DDR). A memory controller communicates with the memory, generates an SDRAM clock signal, and receives a bi-directional sampling clock signal (DQS). When the memory includes the DDR, the memory generates the DQS. When the memory includes the SDRAM, the DQS is based on the SDRAM clock signal.
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