Integrated circuit memory device with delayed write command processing
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United States of America Patent
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Oct 23, 2007
Grant Date -
Jul 12, 2007
app pub date -
Mar 2, 2007
filing date -
Oct 10, 1997
priority date (Note) -
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Abstract
An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense command followed by a write command. The sense command specifies the sensing of a row of memory cells identified by the row address, and the write command specifies that the memory device receive write data and store the write data at a column location identified by the column address. The write command is posted internally to the memory device after a first delay has transpired from when the write command is received at the second set of pins.
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