Methods and apparatus for maintaining cache coherency

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7287126
APP PUB NO 20050027945A1
SERIAL NO

10630164

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Abstract

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Methods and apparatus for maintaining cache coherency and reducing write-back traffic by using an enhanced MESI cache coherency protocol are disclosed. The enhanced MESI protocol includes the traditional MESI cache states (i.e., modified, exclusive, shared, invalid, and pending) as well as two additional cache states (i.e., enhanced modified and enhanced exclusive). An enhanced modified cache line is a cache line that is different than main memory and a copy of the cache line may be in another cache. An enhanced exclusive cache line is a cache line that is not modified and a copy of the cache line is in another cache in a modified state. Depending on the state of a victimized cache line, an internal inquiry may be issued to other caches and/or a write-back operation may be performed prior to victimizing the selected cache line.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BLVD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Desai, Kiran R Cupertino, CA 5 50

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