System on a chip for packet processing
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United States of America Patent
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-
Oct 30, 2007
Grant Date -
Nov 21, 2002
app pub date -
May 18, 2001
filing date -
May 18, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.
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