Semiconductor memory with virtual ground architecture
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United States of America Patent
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Oct 30, 2007
Grant Date -
Jan 13, 2005
app pub date -
May 27, 2004
filing date -
May 30, 2003
priority date (Note) -
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Abstract
Insulation regions in the manner of STI isolations, which run transversely with respect to the word lines, isolate the source/drain regions of adjacent memory cells. Metallic bit lines are applied on the top side and patterned for example along zigzag lines such that the source/drain regions of a memory transistor which are contact-connected by the bit lines are in each case electrically connected by two mutually adjacent bit lines.
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