Multi-level register bank based configurable ethernet frame parser
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United States of America Patent
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Nov 6, 2007
Grant Date -
Jul 1, 2004
app pub date -
Dec 11, 2002
filing date -
Dec 11, 2002
priority date (Note) -
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Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of match signals in response to an incoming data signal. Each match signal is generated in response to different search criteria. The second circuit may be configured to present a protocol indication signal in response to the plurality of match signals.
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