Wafer level chip stack method
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United States of America Patent
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-
Nov 13, 2007
Grant Date -
Jul 14, 2005
app pub date -
Sep 20, 2004
filing date -
Jan 9, 2004
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Provided is a method by which differently-sized chips may be stacked at the wafer level. The wafer level chip stack method utilizes first and second wafer assemblies that support first and second wafers on adhesive tapes. One or both of the supported wafers may be sawed or otherwise divided to obtain separate first and second chips that remain fixed to respective first ring frames. The first and second wafer assemblies may then be positioned and aligned so that a back surface of the second wafer faces an active surface of the first wafer. Each of the second chips may then be bonded to a corresponding first chip to form a chip stack using an adhesive layer. The chip stacks may then be detached from the wafer assemblies and attached to a substrate.
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