Nonvolatile semiconductor memory device
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United States of America Patent
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Nov 13, 2007
Grant Date -
Aug 17, 2006
app pub date -
Apr 5, 2006
filing date -
Nov 13, 2003
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Abstract
A page mode multi-level NAND-type memory employs two different verify levels per data state and comprises a first data storage circuit which is connected to a memory cell and which stores externally inputted data of a first logic level or a second logic level, a second data storage circuit which is connected to the memory cell and which stores the data of the first logic level or second logic level read from the memory cell, and a control circuit which controls the memory cell and the first and second data storage circuits and which reproduces the externally inputted data and writing the data into the memory cell.
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