Method and apparatus of inter-chip bus shared by message passing and memory access
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United States of America Patent
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Nov 13, 2007
Grant Date -
Jun 6, 2002
app pub date -
May 24, 2001
filing date -
May 24, 2001
priority date (Note) -
Withdrawn
status (Latency Note)
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Abstract
A system of switches having a memory/command bus having a first interface, a second interface and a third interface. A memory is connected to the third interface of the memory/command bus. The memory has a first memory address. A first switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The first switch is connected to the first interface of the memory/command bus. The second switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The second switch is connected to the second interface of the memory/command bus.
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