Method and apparatus for routing packets that have ordering requirements
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 13, 2007
Grant Date -
Feb 24, 2005
app pub date -
Oct 1, 2001
filing date -
Oct 1, 2001
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A method of routing packets includes receiving a first packet, where the first packet has a first ordering requirement with respect to a prior packet that was received before the first packet, allocating a first entry that corresponds to the first packet in a scheduler, where the first entry includes a first indication of the first ordering requirement, and in response to the first indication, selecting the first entry corresponding to the first packet if one or more first resources used by the first packet and one or more second resources that are used by the prior packet but not by the first packet are available. As long as older entries whose resources are available are selected before newer entries, the first entry will be selected after the prior packet's entry due to the inclusion of the first indication in the first entry.
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First Claim
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International Classification(s)
Cited Art Landscape
| Patent Info | (Count) | # Cites | Year |
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| 6396809 Method for signaling in a high speed communication system | 23 | 2000 | |
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| 6959002 Traffic manager for network switch port | 79 | 2001 | |
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| 6674754 Wavelength division multiplexing combined with time division multiplexing using a common time reference | 38 | 2000 | |
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| * 6754222 Packet switching apparatus and method in data network | 34 | 2000 | |
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| * 6950394 Methods and systems to transfer information using an alternative routing associated with a communication network | 58 | 2001 | |
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| * 6745277 Intelligent interleaving scheme for multibank memory | 64 | 2000 | |
| * 6975638 Interleaved weighted fair queuing mechanism and system | 59 | 2000 | |
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| 6768717 Apparatus and method for traffic shaping in a network switch | 34 | 2000 | |
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| * 5991295 Digital switch | 104 | 1996 | |
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| * 6907001 Packet switch for switching variable length packets in the form of ATM cells | 66 | 1999 | |
| * 6570876 Packet switch and switching method for switching variable length packets | 78 | 1999 | |
| * 6304570 Distributed type switching system | 3 | 1999 | |
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| * 6857030 Methods, system and article of manufacture for pre-fetching descriptors | 27 | 2001 | |
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| 5857078 Network for transferring consecutive packets between processor and memory with a reduced blocking time | 5 | 1997 | |
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| 6611519 Layer one switching in a packet, cell, or frame-based network | 123 | 1999 | |
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| * 6714553 System and process for flexible queuing of data packets in network switching | 63 | 1998 | |
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| 5440547 Data-transfer routing management for packet-oriented digital communication system including ATM networks | 227 | 1994 | |
| * 6781994 Distributing ATM cells to output ports based upon destination information using ATM switch core and IP forwarding | 26 | 1999 | |
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| * 5790545 Efficient output-request packet switch and method | 92 | 1996 | |
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| * 6654346 Communication network across which packets of data are transmitted according to a priority scheme | 120 | 1999 | |
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| * 6996099 Network switch having a programmable counter | 27 | 2000 | |
| * 7145869 Method for avoiding out-of-ordering of frames in a network switch | 36 | 2000 | |
| 6735679 Apparatus and method for optimizing access to memory | 165 | 2000 | |
| * 6912637 Apparatus and method for managing memory in a network switch | 73 | 2000 | |
| 6950430 Switch fabric with path redundancy | 6 | 2002 | |
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| * 6760337 Integrated circuit that processes communication packets with scheduler circuitry having multiple priority levels | 25 | 2000 | |
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| 6542502 Multicasting using a wormhole routing switching element | 51 | 1996 | |
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| 7002926 Isochronous switched fabric network | 205 | 2000 | |
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| 6417944 Asynchronous transfer mode switch utilizing optical wave division multiplexing | 20 | 1998 | |
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| * 5970229 Apparatus and method for performing look-ahead scheduling of DMA transfers of data from a host memory to a transmit buffer memory | 28 | 1996 | |
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| * 6687247 Architecture for high speed class of service enabled linecard | 286 | 1999 | |
| 6484224 Multi-interface symmetric multiprocessor | 174 | 1999 | |
| * 6977930 Pipelined packet switching and queuing architecture | 96 | 2000 | |
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| 6295295 Scheduler for an information packet switch | 53 | 1998 | |
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| * 5379297 Concurrent multi-channel segmentation and reassembly processors for asynchronous transfer mode | 191 | 1992 | |
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| * 5892766 Method and apparatus for coordinating access to an output of a routing device in a packet switching network | 118 | 1996 | |
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| * 5905998 Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system | 95 | 1997 | |
| 6940814 System and method for a quality of service in a multi-layer network element | 61 | 1999 | |
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| * 6650651 System and method to implement a packet switch output buffer | 6 | 1999 | |
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| * 5974518 Smart buffer size adaptation apparatus and method | 89 | 1997 | |
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| * 6421769 Efficient memory management for channel drivers in next generation I/O system | 28 | 1999 | |
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| * 5901147 Apparatus and methods to change thresholds to control congestion in ATM switches | 56 | 1996 | |
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| * 7042891 Dynamic selection of lowest latency path in a network switch | 17 | 2001 | |
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| 5915104 High bandwidth PCI to packet switched router bridge having minimized memory latency | 68 | 1997 | |
| * 6553446 Modular input/output controller capable of routing packets over busses operating at different speeds | 41 | 1999 | |
| * 6751698 Multiprocessor node controller circuit and method | 88 | 1999 | |
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| 6661774 System and method for traffic shaping packet-based signals | 31 | 1999 | |
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| 5918074 System architecture for and method of dual path data processing and management of packets and/or cells and the like | 131 | 1997 | |
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| 4727537 Flow control arrangement for the transmission of data packets to a communication network | 98 | 1985 | |
* Cited By Examiner
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | May 13, 2019 |
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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