Dual edge command in DRAM
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United States of America Patent
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Nov 20, 2007
Grant Date -
Aug 4, 2005
app pub date -
Jan 29, 2004
filing date -
Jan 29, 2004
priority date (Note) -
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Abstract
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.
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