Model stamping matrix check technique in circuit simulator

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United States of America Patent

PATENT NO 7299428
APP PUB NO 20050177807A1
SERIAL NO

10773541

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Abstract

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The present invention includes a method for detecting model stamping errors during circuit simulation without the need for golden data. The method checks for model stamping errors by determining whether entries in model stamping matrices interrelate according to a plurality of preset rules before circuit equations are solved.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Liu, Zhihong Cupertino, CA 116 505
Ma, Yutao San Jose, CA 23 125
McGaughy, Bruce Fremont, CA 5 19

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