Embedding memory within tile arrangement of a configurable IC
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United States of America Patent
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Nov 27, 2007
Grant Date -
Oct 18, 2007
app pub date -
Mar 15, 2005
filing date -
Mar 15, 2005
priority date (Note) -
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Abstract
Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. Each memory tiles includes a set of routing circuits and a memory array for storing data on which the logic circuit perform computation. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.
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