Sram controller for parallel processor architecture including a read queue and an order queue for handling requests
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United States of America Patent
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Dec 4, 2007
Grant Date -
Aug 19, 2004
app pub date -
Feb 10, 2004
filing date -
Aug 31, 1999
priority date (Note) -
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Abstract
A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.
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