Serial implementation of assertion checking logic circuit
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United States of America Patent
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Dec 4, 2007
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N/A
app pub date -
Feb 4, 2005
filing date -
Feb 4, 2005
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Abstract
Serial assertion checking is realized in a System On a Chip (SoC) device by connecting scan chain output to a bit extractor configured within a functionally reconfigurable module that is part of the SoC, which extracts the bits necessary for the assertion checking. The extracted bits are applied to a finite state machine that implements the assertion checking.
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