Scalable planar DMOS transistor structure and its fabricating methods
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United States of America Patent
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Dec 11, 2007
Grant Date -
Jun 22, 2006
app pub date -
Dec 20, 2004
filing date -
Dec 20, 2004
priority date (Note) -
Expired
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Abstract
The scalable planar DMOS transistor structure of the present invention comprises a scalable source region surrounded by a planar gate region. The scalable source region comprises a p-base diffusion region being formed in a n.sup.- epitaxial semiconductor layer through a ring-shaped implantation window, a n.sup.+ source diffusion ring being formed in a surface portion of the p-base diffusion region through the ring-shaped implantation window, a p.sup.+ contact diffusion region being formed in a middle semiconductor surface portion through a self-aligned implantation window being surrounded by the ring-shaped implantation window, and a self-aligned source contact window being formed on the p.sup.+ contact diffusion region and the n.sup.+ source diffusion ring surrounded by a sidewall dielectric spacer. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being formed on a gate dielectric layer and capped locally with or without metal silicide layers.
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