Logic circuit, system for reducing a clock skew, and method for reducing a clock skew
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United States of America Patent
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-
Dec 18, 2007
Grant Date -
Mar 16, 2006
app pub date -
Mar 2, 2005
filing date -
Sep 15, 2004
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A logic circuit includes a first flip-flop configured to include a first input terminal introducing a clock, a first output terminal supplying the clock and a first internal wiring connecting the first input terminal and the first output terminal, and a second flip-flop configured to be adjacent to the first flip-flop and be supplied with the clock from the first output terminal.
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