Memory hub tester interface and method for use thereof
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United States of America Patent
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Dec 18, 2007
Grant Date -
Dec 22, 2005
app pub date -
Jun 4, 2004
filing date -
Jun 4, 2004
priority date (Note) -
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Abstract
A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command, address, and data signals in accordance with the test command packets, and the memory device command, address, and data signals are provided to a memory device under test that is coupled to the memory hub responsive to a memory device clock signal having a memory device clock frequency.
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