Iterative decoder employing multiple external code error checks to lower the error floor

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United States of America Patent

PATENT NO 7310768
APP PUB NO 20040261002A1
SERIAL NO

10892738

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Abstract

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Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the `BER floor` that is sometimes problematic with conventional turbo decoders.

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Patent Owner(s)

Patent OwnerAddress
ENTROPIC COMMUNICATIONS LLC1345 AVENUE OF THE AMERICAS 46TH FLOOR NEW YORK NY 10105

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Eidson, Donald Brian La Jolla, CA 33 1601
Krieger, Abraham San Diego, CA 21 670
Murali, Ramaswamy San Diego, CA 25 1692

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