Method of manufacturing semiconductor device

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United States of America Patent

PATENT NO 7312133
SERIAL NO

11075022

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method of manufacturing a lateral trench-type MOSFET exhibiting a high breakdown voltage and including an offset drain region around a trench. Specifically, impurity ions are irradiated obliquely to the side wall of a trench to implant the impurity ions only into to the portion of a semiconductor substrate along the side wall of trench, impurity ions are irradiated in parallel to the side wall of trench to implant the impurity ions only into to the portion of semiconductor substrate beneath the bottom wall of trench; the substrate is heated to drive the implanted impurity ions to form an offset drain region around trench and to thermally oxidize semiconductor substrate to fill the trench 2 with an oxide. Alternatively, the semiconductor substrate is oxidized to narrow trench with oxide films leaving a narrow trench and the narrow trench left is filled with an oxide. Still alternatively, a plurality of trenches is formed, the trenches are filled with an oxide and the extended portion of semiconductor substrate extended between the adjacent trenches is converted to an oxide film by thermal oxidation.

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Patent Owner(s)

Patent OwnerAddress
FUJI ELECTRIC HOLDINGS CO LTDKANAGAWA KANAGAWA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kitamura, Akio Nagano, JP 59 751

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