Fault tolerant computer
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United States of America Patent
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Jan 8, 2008
Grant Date -
Aug 5, 2004
app pub date -
May 6, 2003
filing date -
May 15, 2002
priority date (Note) -
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Abstract
A new method for the detection and correction of errors or faults induced in a computer or microprocessor caused by external sources of single event upsets (SEU). This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long instruction word (VLIW) style microprocessors provide externally controllable parallel computing elements which can be used to combine time redundant and spatially redundant fault error detection and correction techniques. This method is completed in a single microprocessor, which substitute for the traditional multi-processor redundancy techniques, such as Triple Modular Redundancy (TMR).
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