System and method for providing error check and correction in memory systems
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United States of America Patent
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Feb 5, 2008
Grant Date -
Nov 25, 2004
app pub date -
Jan 30, 2004
filing date -
Mar 8, 2000
priority date (Note) -
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Abstract
A system for providing error check and correction (ECC) is provided. The system includes an ECC interface for storing ECC codes in a first memory system and storing data in a second memory system. The ECC interface corrects errors in the data received from the second memory system utilizing the ECC codes received from the first memory system. The ECC interface asserts at least one error flag upon detecting errors in the data, and a processor monitors the at least one error flag and corrects the data stored in the first memory system.
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