Testing system and method for memory modules having a memory hub architecture
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United States of America Patent
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Feb 5, 2008
Grant Date -
Feb 15, 2007
app pub date -
Aug 1, 2005
filing date -
Aug 1, 2005
priority date (Note) -
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Abstract
A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method includes a test interface circuit having a memory interface that is coupled to transmit and receive memory signals to and from a tester through a memory bus. The test interface circuit couples test signals to the memory hub in the memory module through a communications link responsive to command, address and data signals received from the tester. The test interface circuit also receives signals from the memory hub in the memory module through the communications link that are indicative of the response of the memory module to the test signals. The test interface circuit then provides corresponding results data to the tester.
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