Error correction within a cache memory
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United States of America Patent
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Feb 5, 2008
Grant Date -
Aug 25, 2005
app pub date -
Jul 1, 2004
filing date -
Dec 18, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
A cache memory includes error bits corresponding to each line of data. An error detecting circuit uses these error bits to detect if a soft error has occurred within the data of a cache line. If such an error has occurred, then the line may be refilled from the main memory or some other action taken, such as a write back or generation of a soft error abort signal.
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