NANO-electronic memory array
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United States of America Patent
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Feb 12, 2008
Issued Date -
N/A
app pub date -
Feb 23, 2005
filing date -
Apr 6, 2004
priority date (Note) -
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Abstract
Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assemblying one or more NANO-elements; and bonding the NANO-elements to the NANO-bonding areas.
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