Integrated circuit memory device having delayed write timing based on read response time
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United States of America Patent
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-
Feb 12, 2008
Grant Date -
Oct 18, 2007
app pub date -
Mar 27, 2007
filing date -
Oct 10, 1997
priority date (Note) -
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Abstract
An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating the write operation in the memory device. A second set of pins output the read data after a first delay time transpires from when the read command is received. Each pin of the second set of pins outputs two bits of read data during a clock cycle of the clock signal. The second set of pins also receive write data after a second delay time has transpired from when the write command is received. The second delay time is based on the first delay time.
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