Optimization of integrated circuit device I/O bus timing
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United States of America Patent
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Feb 19, 2008
Grant Date -
Aug 5, 2004
app pub date -
Jan 20, 2004
filing date -
Jun 29, 2000
priority date (Note) -
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Abstract
The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center of a data packet to produce an alignment offset signal and adjusting the first clock signal using a variable delay device in response to the alignment offset signal to substantially align the edge of the first clock signal to the center of the data packet. Other embodiments are claimed and described.
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