Optimization of die placement on wafers

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7334205
SERIAL NO

10995903

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method of optimizing production of semiconductor devices on a wafer comprises steps of characterizing at least one effect of at least one manufacturing component on at least one optimization criterion; inputting user optimization data; and, based on the at least one effect and the user optimization data, performing optimization to determine a layout of semiconductor devices on the wafer that optimizes performance according to the user optimization data.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
PDF SOLUTIONS INC2858 DE LA CRUZ BOULEVARD SANTA CLARA CA 95050

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cadouri, Eitan Cupertino, CA 17 301

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation