Fault processing for direct memory access address translation
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United States of America Patent
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Mar 4, 2008
Grant Date -
Apr 6, 2006
app pub date -
Sep 30, 2004
filing date -
Sep 30, 2004
priority date (Note) -
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Abstract
An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.
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