System and method for multi-channel delay cell based clock and data recovery
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United States of America Patent
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Mar 11, 2008
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N/A
app pub date -
Jun 28, 2006
filing date -
Jun 28, 2006
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Abstract
Systems and methods regarding the restoration of serialized data to parallel data with a low speed reference signal are provided. In exemplary embodiments, a phased lock loop receives a reference clock signal from a data source and generates a reference high speed clock signal based on the reference clock signal. A dynamic link library clock and data recovery module reads and writes data flows contained within serialized data onto parallel data paths at a modified high speed clock signal based on the reference high speed clock signal.
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