Techniques for sequentially transferring data from a memory device through a parallel interface
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United States of America Patent
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Mar 11, 2008
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N/A
app pub date -
Sep 26, 2003
filing date -
Sep 26, 2003
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Abstract
Techniques are provided for synchronously transmitting data in parallel from an external memory device to a destination circuit using a sequential read mode. The memory device includes an address counter. The address counter generates sequential read addresses for the data bits stored in the memory device. The destination circuit generates a clock signal that controls the address counter. The destination circuit can also transmit a start address to the memory device. The address counter sequentially generates a new read address in response to transitions in the clock signal beginning with the start address. Data bits are transferred in parallel from the memory device to the destination circuit.
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