Method and system for generating a bitstream view of a design
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United States of America Patent
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Mar 11, 2008
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N/A
app pub date -
Aug 12, 2004
filing date -
Aug 12, 2004
priority date (Note) -
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Abstract
A method and system for generating a bitstream view of a programmable logic device (PLD) design are disclosed. The present invention allows for the correlation of a physical circuit description (e.g., one or more of a PLD design's essential configuration bits) and a logical circuit description (e.g., one or more of the logic elements that make up a PLD design), which can also be viewed as correlating one or more of the physical elements of the design's implementation in the PLD with one or more of the design's logical elements.
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