Hardware acceleration of high-level language code sequences on programmable devices
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 18, 2008
Grant Date -
N/A
app pub date -
Sep 28, 2005
filing date -
Sep 28, 2005
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A designer efficiently selects one or more code sequences for acceleration. A hardware accelerator is generated with multiple master ports to allow efficient access to memory. Profiling information can be provided to allow efficient selection of code sequences.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully