Apparatus and methods for adjusting performance of programmable logic devices
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United States of America Patent
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Mar 25, 2008
Grant Date -
Nov 24, 2005
app pub date -
May 19, 2004
filing date -
May 19, 2004
priority date (Note) -
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Abstract
A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).
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