ULTRA HIGH-SPEED NOR-TYPE LSDL/DOMINO COMBINED ADDRESS DECODER
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United States of America Patent
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Mar 25, 2008
Grant Date -
Apr 10, 2008
app pub date -
Oct 5, 2006
filing date -
Oct 5, 2006
priority date (Note) -
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status (Latency Note)
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Abstract
An ultra high speed address decoder uses a combination of Domino logic circuits and LSDL logic circuits. N address hits are converted into N logic true address bits and N complementary address bits. A partial address decoder generates two bit groups using selected of the N logic true address bits and N complementary address bits in NOR logic structures such only two cascaded NFETS are used in a logic tree. The bit groups are partitioned to optimize the layout of the parallel bit lines in the address decoder.
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