Packet receiver with the influence of jitter and packet losses reduced before a buffer becomes idle due to data delays and packet receiving method using the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 25, 2008
Issued Date -
N/A
app pub date -
Nov 2, 2000
filing date -
Mar 27, 2000
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A packet receiver includes a packet memory circuit for temporarily storing received packets in a FIFO (First-In First-Out) fashion in the form of a queue. A read start threshold setting circuit sets, with respect to the length of the queue, a read start threshold at which the received packets should begin to be read out. A read comparing circuit determines whether or not the length of the queue has reached the read start threshold, and outputs a read command signal in accordance with the result of decision. In response to the read command signal, a read control circuit causes the received packets to be read out of the packet memory circuit. The packet receiver reduces the influence of the jitter of a communication network on speech quality. Also, the packet receiver reduces the influence of delays of packets by executing discard processing with the queue.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully