Inter integrated circuit extension via shadow memory
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United States of America Patent
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Apr 1, 2008
Grant Date -
Jun 15, 2006
app pub date -
Dec 13, 2004
filing date -
Dec 13, 2004
priority date (Note) -
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Abstract
Embodiments of the present invention include a system for accessing a memory device comprising a master device coupled to a first serial bus. The system further comprises a slave device coupled to a second serial bus wherein the slave device comprises a first memory. The system further includes a slave device simulator coupled to the first serial bus and coupled to a long distance system specific interconnection, wherein the slave device simulator comprises a first shadow memory of the first memory and wherein a master device simulator is coupled to the second serial bus and coupled to the system specific interconnection. The master device comprises a second shadow memory of the slave device. Data read operations of the master may be satisfied directly from the slave device simulator shadow memory. Data writes from the master are propagated to the slave device and data coherency routines update the shadow memories accordingly.
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