Circuit and method for generating programmable clock signals with minimum skew
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United States of America Patent
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Apr 1, 2008
Grant Date -
Oct 12, 2006
app pub date -
Apr 7, 2005
filing date -
Apr 7, 2005
priority date (Note) -
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Abstract
A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable clock deskewer includes: an output clock generator, responsive to the input clock and control information, to generate the deskewed output clock; and a controller, responsive to the input clock, to generate the control information for controlling the frequency of the deskewed output clock. The programmable clock deskewer may be used to implement a clock tree with various clock outputs for a system on chip integrated circuit.
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