US Patent No: 7,353,486

Number of patents in Portfolio can not be more than 2000

Data processing in digital systems

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ALSO PUBLISHED AS: 20060070016
ATTORNEY / AGENT: (SPONSORED)
 

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Abstract

A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can be formed in the FPGA via a first local IO (Input/Output) circuit and moved to a second local IO circuit. Within each functional block, a mapped logic location function calculates the direction, distance, and the time for the step from the current location of the functional block stored in a mapped location register, and the destination stored in a mapped destination register, and the time allowed for the movement, and stores the direction and distance of the step in the mapped movement register. Then, the functional block moves according the direction and distance stored in the mapped movement register.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTERNATIONAL BUSINESS MACHINES CORPORATIONARMONK, NY68180

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Goodnow, Kenneth J Essex, VT 133 421
Ogilvie, Clarence R Huntington, VT 79 256
Ventrone, Sebastian T South Burlington, VT 224 825

Cited Art

Patent Info (Count) # Cites Year
 
XILINX, INC. (9)
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6,205,574 Method and system for generating a programming bitstream including identification bits 47 1998
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6,629,308 Method for managing database models for reduced programmable logic device components 128 2000
6,346,824 Dedicated function fabric for use in field programmable gate arrays 147 2000
6,530,070 Method of constraining non-uniform layouts using a uniform coordinate system 9 2001
6,836,842 Method of partial reconfiguration of a PLD in which only updated portions of configuration data are selected for reconfiguring the PLD 27 2001
6,624,654 Methods for implementing circuits in programmable logic devices to minimize the effects of single event upsets 9 2002
6,772,405 Insertable block tile for interconnecting to a device embedded in an integrated circuit 5 2002
 
INTEL CORPORATION (2)
6,349,346 Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit 85 1999
6,282,627 Integrated processor and programmable data path chip for reconfigurable computing 214 2000
 
AGILENT TECHNOLOGIES, INC. (1)
5,654,650 High throughput FPGA control interface 52 1995
 
ALCATEL CANADA INC. (1)
2003/0119,555 System for providing fabric activity switch control in a communications system 6 2001
 
ALTERA CORPORATION (1)
6,011,406 Ultra-fast configuration mode for a programmable logic device 15 1998
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
6,996,795 Data processing in digital systems 1 2003
 
STMICROELECTRONICS, INC. (1)
6,577,158 Interconnect circuitry for implementing bit-swap functions in a field programmable gate array and method of operation 7 2001
 
THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE AIR FORCE (1)
6,215,327 Molecular field programmable gate array 35 1999
 
VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY (1)
5,828,858 Worm-hole run-time reconfigurable processor field programmable gate array (FPGA) 129 1996
 
YAMAHA CORPORATION (1)
2003/0023,649 Digital filtering method and device and sound image localizing device 1 2002

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