US Patent No: 7,353,486

Number of patents in Portfolio can not be more than 2000

Data processing in digital systems




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A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can be formed in the FPGA via a first local IO (Input/Output) circuit and moved to a second local IO circuit. Within each functional block, a mapped logic location function calculates the direction, distance, and the time for the step from the current location of the functional block stored in a mapped location register, and the destination stored in a mapped destination register, and the time allowed for the movement, and stores the direction and distance of the step in the mapped movement register. Then, the functional block moves according the direction and distance stored in the mapped movement register.

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Inventor Name Address # of filed Patents Total Citations
Goodnow, Kenneth J Essex, VT 111 731
Ogilvie, Clarence R Huntington, VT 75 426
Ventrone, Sebastian T South Burlington, VT 193 1351

Cited Art Landscape

Patent Info (Count) # Cites Year
Yamaha Corporation (1)
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Altera Corporation (1)
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* 6,530,070 Method of constraining non-uniform layouts using a uniform coordinate system 9 2001
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6,624,654 Methods for implementing circuits in programmable logic devices to minimize the effects of single event upsets 12 2002
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The United States of America as represented by the Secretary of the Air Force (1)
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* Cited By Examiner

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