Modular test controller with BIST circuit for testing embedded DRAM circuits
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United States of America Patent
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Apr 8, 2008
Grant Date -
May 27, 2004
app pub date -
Nov 26, 2002
filing date -
Nov 26, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A modular test controller with a built-in self-test (BIST) circuit for testing an embedded DRAM (eDRAM) circuit is provided. The test controller includes a built-in self-test (BIST) core for performing tests, the BIST core including proven testing algorithms; a selectable tester interface for interfacing the BIST core with an external tester; and a selectable eDRAM interface for interfacing the BIST core with an eDRAM, the eDRAM including a plurality of memory cells for storing data. The present invention allows semiconductor device designers to keep to one testflow and reuse a proven BIST core over multiple ASIC (Application Specific Integrated Circuits) products/generations.
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