Importance

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Abstract

A semiconductor memory module (1) includes a circuit substrate (2), a first (100), a second (200), a third (300) and a fourth (400) rank of memory chips (3), a first register (10) and a second register (20). The first register (10) and the second register (20) each comprise a first input (11, 21) for receiving a respective chip select signal (CS0, CS2), a second input (12, 22) for receiving a respective other chip select signal (CS1, CS3) at least one third input (13, 23) for receiving command/address signals (CA), and at least one third output (16, 26). The at least one third output (16, 26) of the respective first (10) and second (20) register transmits the command/address signals (CA), if at least one of the respective chip select signal (CS0, CS2) received at the respective first input (11, 21) of the respective register (10, 20) and the respective other chip select signal (CS1, CS3) received at the respective second input (12, 22) of the respective register (10, 20) is active, and blocks a transmission of the command/address signals (CA), if both the respective chip select signal (CS0, CS2) received at the respective first input (11, 21) of the respective register (10, 20) and the respective other chip select signal (CS1, CS3) received at the respective second input (12, 22) of the respective register (10, 20) are inactive.

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First Claim